A PMOS transistor includes a p-type drain and source formed in an n-type body. Holes are thus the majority carrier in a PMOS channel. In complementary MOS (CMOS) technology, the bulk substrate is p-type such that the n-type body for a PMOS transistor exists as an n-type well (n-well) in the p-type substrate.
Because holes are the majority carrier in a PMOS transistor, the PMOS source will be at a positive voltage with regard to the drain when the channel is conducting. This positive voltage on the source can be problematic in that a p-n junction is formed between the source and the n-well for the PMOS transistor. If the source is sufficiently biased with regard to the n-well, that p-n junction is then forward biased. A conducting parasitic structure results from this forward biased p-n junction and the ground connection to NMOS transistors in the p-type substrate. The resulting short circuit condition in the conducting parasitic structure is referred to as latchup. Latchup is dangerous in that the circuit can be destroyed from the latchup currents. Moreover, even if the circuit can withstand the short circuit currents, latchup inhibits normal operation.
To prevent latchup, it is conventional to tie a PMOS transistor's n-well to the highest expected voltage. For example, if a PMOS transistor can operate in a low-voltage mode and also in a high-voltage mode, it is conventional to tie the PMOS n-well to the high-voltage supply used during the high-voltage mode operation. But the n-well tie is problematic as transistor dimensions are reduced such as in deep sub-micron technology. At these modern process nodes, the gate oxide is too thin and the transistor is too small to handle the stress resulting from tying the n-well to a relatively high-voltage supply.
To solve the latchup problem for PMOS transistors in modern process nodes that can operate in both high and low voltage modes, it is conventional to use robust PMOS transistors. In other words, the transistor dimensions are increased and a relatively thick gate oxide is used. Such a large thick-gate oxide PMOS transistor can then have its n-well tied to the high-voltage supply without stressing the transistor. But the large transistor dimensions demand a lot of die area relative to the smaller transistor dimensions used in modern process nodes.
Accordingly, there is a need in the art for latchup prevention architectures with increased density.